Aarch64: Drop ISBs in enableFpu/disableFpu

Doing an ISB is very expensive, about ~30 cycles on some CPUs, so try to avoid them if possible.

For the writes to (most) system registers to be observed, a ‘Context Synchronization event’ needs to occur (see ARM DDI 0487 M.a §D24.1.2.2 / pD24-8367).

The kernel is not doing any FPU operations after disabling the FPU, so there is never a need for an ISB there. Returning to user space counts as a ‘Context Synchronization event’ and ensures the FPU enable or disable has completed when user space starts executing.

An ISB after enabling the FPU is only needed in case the FPU was disabled for the kernel and the kernel wants to do FPU operations like saving or restoring the FPU state. The ISB ensures that the FPU enable system register write is finished before FPU using instructions are executed.

For Aarch64 non-HYP it is possible to disable the FPU for user space (EL0), but keep it enabled for the kernel (EL1). This is done by setting CPACR_EL1.FPEN to 1, which the code actually already did.

Aarch64 with virtualisation enabled is more complicated and needs higher level changes to achieve the same, which aren’t done here, the change is limited to removing the ISB in disableFpu().

This partially fixes issue #1569.