# install only available packages in `requirements.txt` using Conda
FOR /F "delims=~" %f in (requirements.txt) DO conda install --yes "%f"
# hspicefile provides a simple function to read hspice binary output files
pip install hspicefile
# CuPy is a NumPy/SciPy-compatible array library for GPU-accelerated computing with Python
pip install cupy-cuda111 # 需指定正确CUDA版本
将金属互连网络等效为寄生网络模型。以Calibre xRC为例，通过电气规则检查(Layout Versus Schematic, LVS)后，采用门级提取方式获得物理版图的寄生参数信息，输出详细标准寄生格式(Detailed Standard Parasitic Format, DSPF)的寄生参数文件，详见src/Data Preparation/rcx文件夹。
generate_lvs_rule.py
optional arguments:
[ --help ] see help
[ --def_path ] Path to the def file, should end in .def
[ --hcell_path ] Path to the output hcell file
[ --xcell_path ] Path to the output xcell file
[ --lvs_rule_path ] Path to the output lvs_rule file
process_vcd_file.py
optional arguments:
[ --help ] see help
[ --vcd_init_path ] Path to the init vcd file, should end in .vcd
[ --vcd_final_path ] Path to the output vcd file
[ --header_path ] Path to the header vcd file
[ --start_time_point ] Start time point for power analysis, timescale 1ns/1ps
[ --num_plaintexts ] Amount of the required plaintexts
[ --desired_time_interval ] Desired time slice for power analysis, timescale 1ns/1ps
[ --off_time_interval ] Time interval between two-times power analysis, timescale 1ns/1ps
generate_ptpx_tcl.py
optional arguments:
[ --help ] see help
[ --ptpx_tcl_path ] Path to the template ptpx file, should end in .tcl
[ --output_tcl_path ] Path to the output ptpx file, should end in ptpx
[ --start_time_point ] Start time point for power analysis, timescale 1ns/1ns
[ --num_plaintexts ] Amount of the required plaintexts
[ --desired_time_interval ] Desired time slice for power analysis, timescale 1ns/1ns
[ --ptpx_run_path ] Path to the run folder of ptpx
logic_cell_modeling.py
optional arguments:
[ --help ] see help
[ --top_cell ] Top cell in the design
[ --parasitic_netlist_path ] Path to the parasitic info file, should end in .dspf
[ --def_path ] Path to the def file, should end in .def
[ --power_report_path ] Path to the power report file, should end in .out
[ --num_plaintexts ] Number of the required plaintexts
[ --start_time_point ] Start time point in the initial power report
[ --desired_time_interval ] Desired time interval to use, timescale 1ns/1ns
[ --desired_time_scale ] Desired time scale used in power analysis
[ --power_report_init_path ] Path to the init power report file, should end in vcd_
[ --power_supply_voltage ] Supply voltage for logic cells
logic_cell_to_current_source.py
optional arguments:
[ --help ] see help
[ --lc_currents_path ] Path to the simulated logic cell currents
[ --cell_name_path ] Path to the Reorder cell name from dspf file
[ --power_port ] VDD and VSS port in physical layout
[ --mark_net ] Start and break net in the .dspf file, should end in a blank
[ --netlist_path ] path to the parasitic netlist, should end in .dspf
[ --desired_time_scale ] Desired time scale used in power analysis
Prep_For_Sim.py
optional arguments:
[ --help ] see help
[ --parasitic_netlist ] Path to the parasitic netlist, should end in .dspf
[ --metal_layers ] Target metal layers
[ --power_port ] VDD and VSS port in physical layout
[ --template_file ] Path to the default sp template file
[ --output_file ] Path to write the final sp to
tr_to_h5.py
optional arguments:
[ --help ] see help
[ --num_plaintexts ] Number of required plaintexts
[ --spice_result_path ] Path to result files from Spice simulation
[ --metal_layers ] Target metal layers
[ --output_file ] Path to final currents across metal wires
Compute_EM_formulation.py
optional arguments:
[ --help ] see help
[ --metal_layers ] Target metal layers
[ --transient_file ] Path to the transient analysis file, should be in csv form
[ --use_gpu ] Allow for gpu acceleration
[ --num_input_stimuli ] Number of required plaintexts for em computation
[ --clock_period_ns ] Amount of sample points per input stimuli
[ --start_time_ns ] Start time point in simulation per input stimuli
[ --end_time_ns ] End time point in simulation per input stimuli
[ --target_area_x ] Target simulated area in x axial direction
[ --target_area_y ] Target simulated area in y axial direction
[ --num_probe_x_tiles ] Number of point grid in x axial direction
[ --num_probe_y_tiles ] Number of point grid in y axial direction
[ --num_probe_z_tiles ] Number of point grid in z axial direction
[ --layout_max_z ] Target simulated distance in z axial direction, option value = true value x 2
[ --num_horizontal_tiles_per_wire ] Number of horizontal tiles per metal wire
[ --num_vertical_tiles_per_wire ] Number of vertical tiles per metal wire
[ --ns_per_sample ] Simulated value of time scale per sample point
[ --output ] Path to write the output
[ --layout_min_x ] Reference coordinate in x axial direction
[ --layout_min_y ] Reference coordinate in y axial direction
EMSim是一款版图级芯片电磁仿真器，基于物理版图预测集成电路的电磁行为，辅助芯片电磁安全的硅前量化与验证，由天津大学智能感知与安全技术实验室开源和维护。
智能感知与安全技术实验室是国内第一批在硬件安全领域开展研究的团队，研究领域包括集成电路硬件安全、密码芯片设计与安全分析、硬件形式化建模与验证、面向智能传感的混合信号芯片与系统设计等方面。
该工作正式发布于，2022年7月30日，第一届中国计算机学会芯片大会(CCF Chip)暨openDACS v2.0-EDA开源论坛。
若有任何意见或建议，欢迎通过issues或邮件(dochejj@tju.edu.cn, hc_ma@tju.edu.cn, jinyier@gmail.com)与我们联系。
环境配置
操作系统：Linux or Windows
EDA软件：VCS, Calibre xRC, PrimeTime PX, HSpice
依赖项：Python 3.8+ with PIP
实现框架
EMSim的实现框架包含数据准备、电流分析和电磁计算过程。基于版图数据库，EMSim执行多级电路分析来获得物理版图的电流分布。根据电磁场理论，EMSim将瞬态电流转化为空间任意观测点的磁场数据。
数据准备
创建版图数据库是EMSim的首要环节，由RTL-to-GDS设计流程实现，作为后续电流分析和电磁计算的输入数据。
电流分析
在电流分析环节，EMSim将逻辑单元的翻转活动等效为随时间变化的电流源激励，将片上电源网络和信号互连线等效为寄生网络模型，最终将上述模型融合为整个芯片的电气模型，通过Spice仿真获得物理版图上的瞬态电流分布。
寄生网络模型
将金属互连网络等效为寄生网络模型。以Calibre xRC为例，通过电气规则检查(Layout Versus Schematic, LVS)后，采用门级提取方式获得物理版图的寄生参数信息，输出详细标准寄生格式(Detailed Standard Parasitic Format, DSPF)的寄生参数文件，详见
src/Data Preparation/rcx文件夹。generate_lvs_rule.py创建Hcell、Xcell文件和LVS BOX命令语句，Hcell文件指定用于门级提取的单元列表，Xcell文件定义视作理想器件的单元列表，其内部不再经历寄生参数提取。PEX规则文件添加LVS BOX命令语句，将上述单元以黑盒形式处理，同时手动禁用电路使用的器件类型。单元级电流源
将逻辑单元建模为电流源激励，分为动态门级仿真和单元功耗分析两个步骤。
动态门级仿真旨在获得逻辑单元的翻转活动。以Synopsys VCS工具为例，仿真过程将SDF文件反标到版图后门级网表，在特定测试激励条件下，记录单元翻转活动并输出值变转储(Value Change Dump, VCD)文件，详见
src/Data Preparation/sim/postsim文件夹。process_vcd_file.py按测试激励顺序切割tb_main.vcd文件并输出到vcd_files文件夹，作为单元功耗分析的输入。generate_ptpx_tcl.py基于ptpx.tcl模板文件创建对应测试激励顺序的ptpx_files文件夹，作为单元功耗分析的输入。ptpx.tcl中输入数据的文件路径。ptpx.tcl的波形精度，参考-set_power_analysis_options -waveform_interval命令。单元功耗分析旨在获得逻辑单元的实时功耗。以Synopsys PrimeTime PX工具为例，导入设计数据和工艺库信息，包括版图后门级网表、Liberty库文件、SDC文件、SPEF文件和VCD文件，选择瞬态仿真模式在逻辑单元的输出状态发生变化时计算其瞬态功耗，详见
src/Data Preparation/ptpx文件夹。Spice仿真模型
logic_cell_modeling.py和logic_cell_to_current_source.py处理单元级电流源和寄生网络模型，提取物理版图DEF文件和DSPF文件的位置映射关系，将单元级电流源插入到寄生网络模型的内部节点。Prep_For_Sim.py融合了寄生网络模型、单元级电流源和独立电压源，构成了描述芯片拓扑结构和电气行为的Spice仿真模型。对该模型的仿真旨在获得顶层金属层内电源网格的瞬态电流分布。以HSpice工具为例，HSpice使用直接线性求解器求解该方程系统并输出选定金属线的瞬态电流。需要注意的是，直接线性求解器的时间复杂度与电路规模具有超线性关系，改进的求解器如FastSPICE引擎可以进一步加快仿真过程。
template.txt模板文件的诸多仿真设置。电磁计算
tr_to_h5.py将Spice仿真结果final.tr系列文件转化为h5格式的last_binary_run.h5文件，作为电磁计算的输入。Compute_EM_formulation.py采用毕奥-萨伐尔定律计算特定观测点或观测面的芯片磁场分布情况。贡献者
版权声明
It is mainly intended for non-commercial use, such as academic research.
许可证
MIT License, see license in LICENSE.