目录
- .githubAdd Issue/PR Template based off of Chisel/FIRRTL (#1502)6年前
- bootromchange DRAM base6年前
- csrcMerge branch 'master' into merge6年前
- emulatorMerge commit 'a05728c4fab84a13585e14ac684b47c875b17b57' into boom5年前
- fpgaMerge branch 'pcie-ssd' into 'master'5年前
- macrosValName: 'lazy val' now also counts for providing a name7年前
- projectBump firrtl, json4s, and sbt (#1739)6年前
- regressionChange riscv-tools install rule so checkout is an order-requ rather than dependency. This is to6年前
- scriptsMerge remote-tracking branch 'shinezyy/boom' into bump-rocket5年前
- srclvna,LvNAConfigs: add more interrupts for pcie5年前
- vsimMerge branch 'upstream' into merge-upstream6年前
- .gitignoreAdd two types of debug facilities6年前
- .gitmodulesMerge commit 'a05728c4fab84a13585e14ac684b47c875b17b57' into boom5年前
- .travis.ymlBump verilator to v4.008 (#1762)6年前
- LICENSE.Berkeleyscripts: two scripts to determine copyright holder of files8年前
- LICENSE.SiFiveUpdate LICENSE.SiFive (#618)8年前
- LICENSE.jtagAdd ucb-art/chisel-jtag (#612)8年前
- MakefragAdded makefile rules for bootrom image.6年前
- README-rocketchip.mdUpdate readme6年前
- README.mdUpdate readme6年前
- README_LvNA.mdupdate doc6年前
- README_TRAVIS.mdUpdate README_TRAVIS.md7年前
- build.sbtBump firrtl, json4s, and sbt (#1739)6年前
- origin_rocket_README.mdupdate readme6年前
- riscv-tools.hashbumping riscv-tools6年前
- sbt-launch.jarBump chisel and firrtl (#1232)7年前
- chisel3@9a0ce2272cBump chisel36年前
- firrtl@2272044c6aBump firrtl6年前
- hardfloat@45f5ae171abump hardfloat for scala 2.11.12 (#1216)7年前
- torture@77195ab12aMerge with Head8年前
邀请码
Labeled RISC-V based on Rocketchip
We build our labeled RISC-V prototype based on rocketchip.