Bump spike ref in ready-to-run (#97) spike commit: 95d1c4b18036a4bcc2204dcd5aa4544812de3707 spike config: CPU=XIANGSHAN, CPU=NUTSHELL ubuntu 20.04 clang Including: * fix(satp): fix mask of satp.ppn when write to satp and H ext enable (OpenXiangShan/riscv-isa-sim#86)
Bump spike ref in ready-to-run (#97)
Including: * fix(satp): fix mask of satp.ppn when write to satp and H ext enable (OpenXiangShan/riscv-isa-sim#86)
This repo includes some prebuilt workloads and difftest reference libaries. Please refer to XiangShan-doc to learn how to use them.
This repo may be abandoned in feature, as we are trying to provide prebuilt binaries through Github release.
riscv64-nemu-interpreter-so
riscv64-nemu-interpreter-dual-so
riscv64-spike-so
linux.bin
microbench.bin
apps/microbench
coremark-2-iteration.bin
apps/coremark
copy_and_run.bin
apps/loader
flash_recursion_test.bin
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XiangShan ready-to-run binaries
This repo includes some prebuilt workloads and difftest reference libaries. Please refer to XiangShan-doc to learn how to use them.
This repo may be abandoned in feature, as we are trying to provide prebuilt binaries through Github release.
Prebuilt difftest reference libaries
riscv64-nemu-interpreter-so
riscv64-nemu-interpreter-dual-so
riscv64-spike-so
Prebuilt workloads
linux.bin
Built accodring to XiangShan-docmicrobench.bin
apps/microbench
coremark-2-iteration.bin
apps/coremark
copy_and_run.bin
apps/loader
flash_recursion_test.bin