feat(apps): add icache ecc test (#48)
Add test for https://github.com/OpenXiangShan/XiangShan/pull/4044
Example log:
The first instruction of core 0 has commited. Difftest enabled. Setup Hello, World @ 0! Test === [0] Inject metaArray === ECC inject start! eccctrl=0x3 ECC inject done! eccctrl=0x21 No error, call target() Hello, World @ 1! === [0] Test passed! === === [1] Inject dataArray === ECC inject start! eccctrl=0xb ECC inject done! eccctrl=0x29 No error, call target() Hello, World @ 2! === [1] Test passed! === === [2] Inject to invalid target === ECC inject start! eccctrl=0x7 ECC inject done! eccctrl=0xf5 === [2] Test passed! === === [3] Inject when ecc not enabled === ECC inject start! eccctrl=0x2 ECC inject done! eccctrl=0x70 === [3] Test passed! === === [4] Inject to invalid address === ECC inject start! eccctrl=0x3 ECC inject done! eccctrl=0x171 === [4] Test passed! === Core 0: HIT GOOD TRAP at pc = 0x8000031a
The Abstract Machine (AM)
Get Started for Memory Images (Workloads)
In this section, we demonstrate how to build memory images (
base_address = 0x80000000
) for simulation.clone
nexus-am
from github:enter tests or benchmark directory (using
apps/coremark
as an example):use the “.bin” file as the memory image for RTL simulation
Here we use the DiffTest RTL-simulation framework as an example. NEMU and other designs should work similarly if the base address is 0x8000_0000.
How to build benchmark flash image
Some designs have a read-only bootrom for bring-up. This section builds the bootrom (flash) image whose base address is 0x1000_0000. We will be using
riscv64-xs-flash
instead ofriscv64-xs
to fix into the new address space. Do NOT follow the steps in this section if you don’t know what the bootrom means.enter benchmark directory (using
apps/coremark
as an example):you will find a “.bin” file, this is a benchmark image for flash
to add the flash image to simulation in DiffTest, you can use the
-F
option:Explanation of multi-processor bring-up drivers
The driver consists of the following functions (implemented in am/src/xs/isa/riscv/mpe.c) :
_mpe_init(void (*entry)())
: register anentry
procedure that each processor will run into after initialization_ncpu()
: return the total number of processors_cpu()
: return the hartID of current processor (start from 0)_atomic_xchg(intptr_t *addr, intptr_t newval)
: atomic exchange function,replace the value in *addr with newval and return the original value_atomic_add(intptr_t *addr, intptr_t adder)
: atomic adding function,increment value in *addr with adder and return the original value_barrier()
: barrier function,wait until all processors arrive here(For more atomic operations, You can implement it yourself using a similar format as _atomic_add)
A simple demo is provided in tests/amtest/src/tests/mp.c Here is the instruction to build and run
The output should be like this:
Note that both
sum
andatomic_sum
are incremented 100 times per CPU parallelly. However,atomic_sum
utilizes atomic primitive. Thus, we havesum
<= 200 &&atomic_sum
== 200.How to build AM image for 16550
The major difference between RTL simulation with Verilator and FPGA of Xiangshan is that FPGA is using 16550 at 0x310b0000, while RTL simulation is using UARTLITE at 0x40600000. So we should change the serial devices when compiling for FPGA by
Then run
build/hello-riscv64-xs.bin
on FPGARemember to
rm -rf $AM_HOME/am/build build
if you want to switch back to uartlite.How to generate compile_commands.json
compile_commands.json
can be used in many language servers to help completion.If you don’t have bear on your machine, please search.