forked from xuos/xiuos
137 lines
3.7 KiB
C
137 lines
3.7 KiB
C
/* generated HAL source file - do not edit */
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#include "hal_data.h"
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#define FSP_NOT_DEFINED (UINT32_MAX)
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#if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
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/* If the transfer module is DMAC, define a DMAC transfer callback. */
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#include "r_dmac_b.h"
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extern void scif_uart_tx_dmac_callback(scif_uart_instance_ctrl_t const *const p_ctrl);
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void g_uart0_tx_transfer_callback(dmac_b_callback_args_t *p_args)
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{
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FSP_PARAMETER_NOT_USED(p_args);
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scif_uart_tx_dmac_callback(&g_uart0_ctrl);
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}
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#endif
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#if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED)
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/* If the transfer module is DMAC, define a DMAC transfer callback. */
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#include "r_dmac_b.h"
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extern void scif_uart_rx_dmac_callback(scif_uart_instance_ctrl_t const *const p_ctrl);
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void g_uart0_rx_transfer_callback(dmac_b_callback_args_t *p_args)
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{
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FSP_PARAMETER_NOT_USED(p_args);
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scif_uart_rx_dmac_callback(&g_uart0_ctrl);
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}
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#endif
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#undef FSP_NOT_DEFINED
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scif_uart_instance_ctrl_t g_uart2_ctrl;
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scif_baud_setting_t g_uart2_baud_setting = {
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/* Baud rate calculated with 0.469% error. */
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.semr_baudrate_bits_b.abcs = 0,
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.semr_baudrate_bits_b.bgdm = 1,
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.semr_baudrate_bits_b.cks = 0,
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.brr = 53,
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.mddr = (uint8_t)256,
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.semr_baudrate_bits_b.brme = false
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};
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/** UART extended configuration for UARTonSCIF HAL driver */
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const scif_uart_extended_cfg_t g_uart2_cfg_extend = {
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.bri_ipl = 14,
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.bri_irq = SCIF2_BRK_IRQn,
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.clock = SCIF_UART_CLOCK_INT,
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.noise_cancel = SCIF_UART_NOISE_CANCELLATION_DISABLE,
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.p_baud_setting = &g_uart2_baud_setting,
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.rx_fifo_trigger = SCIF_UART_RECEIVE_TRIGGER_MAX,
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.rts_fifo_trigger = SCIF_UART_RTS_TRIGGER_14,
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.uart_mode = SCIF_UART_MODE_RS232,
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.flow_control = SCIF_UART_FLOW_CONTROL_NONE,
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.rs485_setting = {
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.enable = (sci_uart_rs485_enable_t)NULL,
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.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
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.de_control_pin = (bsp_io_port_pin_t)SCIF_UART_INVALID_16BIT_PARAM,
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},
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};
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/** UART interface configuration */
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const uart_cfg_t g_uart2_cfg = {
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.channel = 2,
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.data_bits = UART_DATA_BITS_8,
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.parity = UART_PARITY_OFF,
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.stop_bits = UART_STOP_BITS_1,
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.p_callback = NULL,
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.p_context = NULL,
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.p_extend = &g_uart2_cfg_extend,
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.p_transfer_tx = g_uart0_P_TRANSFER_TX,
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.p_transfer_rx = g_uart0_P_TRANSFER_RX,
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.rxi_ipl = 14,
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.txi_ipl = 14,
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.tei_ipl = 14,
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.eri_ipl = 14,
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.rxi_irq = SCIF2_RXI_IRQn,
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.txi_irq = SCIF2_TXI_IRQn,
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.tei_irq = SCIF2_TEI_DRI_IRQn,
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.eri_irq = SCIF2_RERR_IRQn,
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};
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/* Instance structure to use this module. */
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const uart_instance_t g_uart2 = {
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.p_ctrl = &g_uart2_ctrl,
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.p_cfg = &g_uart2_cfg,
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.p_api = &g_uart_on_scif
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};
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mhu_ns_instance_ctrl_t g_mhu_ns0_ctrl;
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const mhu_cfg_t g_mhu_ns0_cfg = {
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.channel = 1,
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.rx_ipl = 12,
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.rx_irq = MHU1_NS_IRQn,
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.p_callback = NULL,
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.p_shared_memory = 0,
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.p_context = NULL,
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};
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/* Instance structure to use this module. */
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const mhu_instance_t g_mhu_ns0 = {
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.p_ctrl = &g_mhu_ns0_ctrl,
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.p_cfg = &g_mhu_ns0_cfg,
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.p_api = &g_mhu_ns_on_mhu_ns
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};
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gtm_instance_ctrl_t g_timer2_ctrl;
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const gtm_extended_cfg_t g_timer2_extend = {
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.generate_interrupt_when_starts = GTM_GIWS_TYPE_DISABLED,
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.gtm_mode = GTM_TIMER_MODE_INTERVAL,
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};
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const timer_cfg_t g_timer2_cfg = {
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.mode = TIMER_MODE_PERIODIC,
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.period_counts = (uint32_t)0x1869f /* Actual period: 0.001 seconds. */,
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.channel = 2,
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.p_callback = NULL,
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.p_context = NULL,
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.cycle_end_ipl = 255,
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.p_extend = &g_timer2_extend,
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#if defined(VECTOR_NUMBER_GTM2_COUNTER_OVERFLOW)
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.cycle_end_irq = VECTOR_NUMBER_GTM2_COUNTER_OVERFLOW,
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#else
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.cycle_end_irq = GTM2_OSTM2INT_IRQn,
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#endif
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};
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/* Instance structure to use this module. */
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const timer_instance_t g_timer2 = {
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.p_ctrl = &g_timer2_ctrl,
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.p_cfg = &g_timer2_cfg,
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.p_api = &g_timer_on_gtm
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};
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void g_hal_init(void)
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{
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g_common_init();
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}
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